The outputs of the CY2308-2 and the CY2308-3 are inverted when operating in bypass mode. This is caused by an extra inverter in the phase compensation circuit. This phase compensation circuit is used when the output banks are split and the two banks are running at different frequencies. There is no phase inversion in the output drivers when the PLL is enabled and the part is used as a Zero Delay Buffer. An application that is using the CY2308-2 and/or CY2308-3 and requires zero phase inversion from the input clock should not use the bypass mode. The CY2308 datasheet does not specifically describe this phase inversion when in PLL bypass mode.