Phase Alignment for the CY22393/4/5

Question: What changes on the input clock can cause the phase change on output clock? Is there any special requirement on the input clock for CY22393 to avoid the phase of output clock unstable?



For the CY22293/4/5, there is an individual divider for each output. The output dividers are always clocked on the rising edge of reference source. There is NO synchronization circuitry included for different dividers. So the outputs reference from the same PLL with dividers, they may NOT be phase aligned.

The outputs will be phase aligned if the outputs reference the same PLL and bypass the output divider (set it to 1). There is also another option, if the output references the same PLL and the divider values are related to each other only by a factor of 1. For example, if you have PLL1 running at 100MHz and have CLKA set to divide by 1 and CLKB set to divide by 2, the 100MHz and 50MHz outputs will be guaranteed to come up phase aligned. This is because 2 and 1 are only related by a factor of 1.

We CANNOT guarantee phase alignment outside of the above cases. The reason is that the output dividers are not synchronized to each other and can power up in random states. The output dividers are always clocked on the rising edge of the reference source.