There is no specification for the input clock duty cycle for CY2305 / CY2305C/ CY2309 / CY2309C. This is due to the way the zero delay buffer (ZDB) works. For every clock cycle, the phase detector will detect the rising edge and compare it with the feedback clock rising edge, and then generate a clean output. Since the PLL locks to the rising edge of the input, the falling edge doesn't really matter and as a result, the output duty cycle will be guaranteed as specified even if the input duty cycle is poor. In this way, the ZDB can correct for bad duty cycle. Usually, even if the input duty cycle is 10-90%, the device should still function.