First, please ensure that the daisy chain has been properly declared in ISR.
Often times, TCK can become degraded when the JTAG chains are long. Therefore, when there are more than 3 devices in the JTAG chain, it becomes a good idea to terminate the signal line. This is discussed in the "Design Considerations for In-System Reprogrammable(TM) (ISR(TM)) Programming of Cypress CPLDs" application note (link below). This signal is a clock signal, and should be treated as such in PCB considerations.
For more information, please refer to the Application Note:
Design Considerations for In-System Reprogrammable(TM) (ISR(TM)) Programming of Cypress CPLDs.
Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development.