In order to clear a pending interrupt it must be serviced, the Interrupt Vector Clear (INT_VC) register must be cleared, or a zero must be written to the appropriate Interrupt Clear (INT_CLRx) register. When servicing an interrupt, the decode logic acknowledges that an interrupt is pending. The logic determines where the ISR is located, in the interrupt vector table, and clears the pending interrupt in the INT_VC register. Lastly, the ISR is taken. Writing a zero to the appropriate INT_CLRx Register will also clear posted interrupts, as long as the Enable Software Interrupt (ENSWINT) bit is also set to zero (see section B:5.3 of the TRM).
The decode logic circuitry clears the pending interrupt in the INT_VC register.