Bank3 can be configured into two pairs of differential outputs by setting the INV3 pin LOW (gnd). In this mode each matched output pair becomes complementary ([3QA0 , 3QA1] and [3QB0 , 3QB1]). The output buffers of Bank3 are designed to have matched delay, pulse width and rise/fall times to emulate a real differential output. While RoboClockII outputs are LVTTL, LVPECL is a 1V logic centered about V and so RoboClockII outputs represent a superset of PECL. If the line receiver has no maximum voltage swing limit then the outputs will be sufficient to drive PECL loads. If the line receiver has a 1V nominal swing, then a combination of series and parallel termination on the line will make them compatible.