LV capture timer interrupt in  enCoRe II

Question: The enCoRe II LV capture timer interrupt seems to happen only for the first edge. How to fix this?



The interrupt status bits in TCAPINTS register [0x2C] must be cleared before subsequent capture timer interrupts can take place. The status bits are cleared by writing 1 to the appropriate status bit location in the register. So, in the capture timer ISR after the timer capture register is read, we need to clear the status bits right before we restore A and X registers and then exit the ISR.