If there is one missing cycle for the reference clock, it would not affect output clock. If reference clock is dead during 100 cycles, it may affect output clock. As you know, the PLL device has Phase Detector (PD) to compare the reference input and feedback input. If the input clock goes dead under PD update rate, it won't affect output clock. But PD update rate will vary with operation frequency. For sure if there is only one missing pulse for input clock, it won't affect output clock. But for 100 cycles, it is hard to predict. So the PLL may lose lock and then relock again when the reference is good.