CY2DP818 LVPECL Driving A 2.5V CMOS Input

Question: How can a 2.5V ASIC be protected when interfacing to the 3.3V CY2DP818?



The JEDEC CMOS 2.5V specification is 1.7V min VIH. If the terminal point is 1.3V then an RTT-VTT load is requried. These are Open Source output devices, so the VOL voltage is user defined with the 50 ohms to 1.3V.

A trace/transmission line runs between the two devices. The line from the CY2DP818 is terminated into the RTT load at the ASIC. Normally the RTT load is a 50-ohm resistor to VTT (1.3V). The special case VTT is GND. Logic and math shows about two-thirds of voltage is needed.

At the ASIC end of the transmission line, place a 1 percent, 16.9 ohm resistor in series with a 34-ohm resistor terminating in GND. Their sum adds up to the typical 50- or 51-ohm term.

At hot and room temperatures, the output will be above the 1.7v min. When at room temperature, LVPECL delivers 2.8 min. Output is 1.8V.

At hot temperatures, 2.2 min output delivers 1.9V, which is still above 1.7v min VIH of 2.5V. At 16.9 ohms and 34 ohms make a voltage divider and still terminate in 50 ohm at the end of the line.

CY2DP818 o-------oooooooo--------/\/\/\/\/\---|--/\/\/\/\--- GND
~~~~~~~~~~~~~~~~~~~~~~~~~~~~|___________asic input(s). or 2.5V logic.