The general family of LVPECL swings from 3.3V as a VDD level, and near ground on the lower end. The actual specs vary across vendors because LVPECL is not based on an I/O standard.
In general, the differential signal is fed into a resistor ladder that translates the higher voltages of LVPECL to that of the lower needsof LVDS. Values can be changed as needed for the application. The LVDS input is specified around a 50-ohm termination at or near the inputs. Sometimes this is a 100-ohm resistor across the inputs. This ladder provides the 50 ohm terminations, the input bias level when the output is a zero, (840mv), and the level shifter, (0.6 * input), and a total line impedance, equivalent impedance to ground of 50 ohms.
The CY2DL814 is a differential to LVDS translator. The resistor tree would be eliminated, except for the two 50/51 ohm resistors. The value of 51 is an EIA standard value. The value of 50 is common.