Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A.

Question: How to avoid RX FIFO overflow in the CY7C924ADX and CY7C9689A?



There are only two ways to prevent receiver FIFO overflow problems:

1. Ensure that the read clock for the receive FIFO is always faster than the received character rate
2. Discard sufficient characters so that the effective character rate is less than the FIFO read clock rate. (Use the discard policy configuration).

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