Question: When we turn off the clock output for the CY22150 Programmable Clock, is there a weak pull down/up to ensure a known level? What is the difference between the two modes interims the output? Can we get a known level at the output?
Answer: The issue is that on one of our ASICs, when we turn off the clock the PLL is sensing the noise on the line since the clock line is floating and then it tries to lock on that thus consuming more power.
If you are using the CY22050, then powering down or using the output enable pin will just leave the outputs floating. But with the CY22150, there is a way to shift in a configuration to disable the outputs and make them drive low.
Using registers 0x09 will tri-state the output. But if you change the CLKSRC2:CLKSRC0 values in registers 0x44 to 0x46 to be 111, it should drive the outputs low. When the CLKSRC bits are set to 111, the outputs are driving out a test signal, which in your case should be disabled so the outputs will be driven low.
