This error occurs when Warp is having difficulty routing the appropriate product terms inside a logic block, due to the signals assigned there. Most commonly, this occurs when designers have locked the pins in that logic block to specific signals, and those signals require too many product terms for the compiler to route correctly. Although it is true that a given macrocell can handle up to 16 product terms, there are limits imposed based on the way that product terms are routed and shared.
Please view the report file and the product term allocation area. The location where there are X's in the same column mean that those equations are sharing the same product term. To have equations requiring truly unique product terms, the product terms must be allocated so that two X's do not appear in the same column.
A possible solution to this would be to not lock the pins at all, or change their locations to allow Warp room to route the appropriate product terms. However, if this is not possible, it is likely that by creating a temporary signal, and forcing Warp to retain it by using synthesis attributes, a large portion of the product terms can be moved to an embedded macrocell. However, if resource utilization is already high, this may also not work.
Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. Also our Warp Software Tool is Obsolete.