A higher VCO frequency will always provide you better jitter performance which we recommend making a part of our rule when we configure our programmable clocks. Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.
So with a lower frequency, either your VCO is running slower which increases jitter, or you are using a larger divider value which can also increase the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.
In cases where reducing jitter is of paramount importance, we recommend running fewer PLLs in case of multi-PLL devices. The typical peak-peak period jitter value totally depends on the configuration of the device, number of outputs in use, output loading. Jitter can be lowered by using the least number of outputs and PLL's. Another parameter is the Q value. Using smaller Q values will also help decrease the peak-peak jitter. Different frequency combinations will yield different P and Q values, and you generally want the lowest P and Q values possible.