Your jitter will be reduced when you minimize the number of PLL's running on the die. The worst case jitter depends on how many outputs and PLL's are running as well as what combinations of frequencies are running on the chip.
Keeping VCO frequencies high as possible will always give you better jitter performance. The way to minimize jitter is to run the minimum number of outputs and PLL's. Also having clean multiples of the input frequency will help reduce jitter in some cases as well.
For more information please refer to our Jitter in PLL Based Systems-Causes, Effects and Solutions-AN1113 application note available on our website.