CY22393 Frequency Array Table: 8x3 registers Register Requirement

Version 1
    Question: Why does the SONOS Frequency Array Table of part CY22393 include 8x3 registers for the configuration of the PLL1 (40h to 57h) when S2 has only 2 bits? The 4x3 registers seem to be sufficient (40h to 4Bh).



    It is necessary to access different table entries for PLL1 depending on the state of the SCLK and SDAT pins at power up. In most cases for I2C, the lines are pulled up so access to table entry 011 and 111 is available by toggling the S2 pin. Write to addresses 49H to 4BH and 55H to 57H to see any changes on the clock outputs referencing PLL1.