CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied.

Question: When the serial inputs to the CY7B933 are left floating and REFCLK of 40MHz is supplied,Why are CKR outputs are unusable?



The 933's inputs are very sensitive to any noise coupling (even down to a few mV). Normally, the CDR will try to track the incoming data stream. If the recovered clock is close enough (within +/-1000ppm), its within the limits and it will stick to the recovered clock. If not, then it shifts to track the REFCLK and then tries to track the data stream again. This process repeats until its stable. Now, at a lower frequency of 20MHz, the noise from the REFCLK line couples with the serial inputs (which are very sensitive) and the CKR can give a stable 20MHz output. At 40MHz, the sensitivity of the outputs decreases drastically (since the inputs have lower bandwidth at higher frequencies) and the noise coupling is not sufficient enough. Hence, the CDR keeps oscillating between the inputs and the REFCLK and does not stabilize. Hence, you have a highly unstable output on CKR.