Jitter on the outputs of the CY2304 or PLL bypassed devices.

Question: Does the CY2304 or PLL bypassed devices introduce jitter on the outputs? What should be done to reduce the jitter on clock distribution below unit level ?



Currently only filtering circuits can be used to reduce device jitter below unit level. If the clock source is purely clean - atomic or that grade, then the outputs can be filtered to reduce noise that is either generated or picked up on the way. These are small RF designs and are application specific.