When using the Slave FIFO interface with SLCS functionality enabled (bits 7 and 6 of the PORTACFG register set to 01b) this pin is configured as an input and must be driven externally. The SLCS pin allows external logic to effectively remove the FX2 from the FIFO Data bus.
When SLCS is de-asserted, the FX2 will ignore all Slave FIFO control signals (SLWR, SLRD/SLOE, PKTEND) and tri-state the data bus. Only the local bus is affected. It is OK to tie SLCS low all the time if you do not need to share the FIFO data bus with any other external peripheral.