Handling Odd Count Packet Sizes Between an FX2-SX2 16-bit WORDWIDE Interface

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    Question: When an odd number of bytes (eg. 45 bytes) are sent from FX2's EP2OUT to SX2's EP6IN, the SX2 receives it in word form and it is considered 23 words, since we are using a 16-bit WORDWIDE interface across the two chips. When the words are converted back to bytes later, the SX2 will multiply it by 2 and becomes 46 bytes in the endpoint FIFO instead of the original 45 bytes originally sent. What should be done to ensure that the byte count in SX2 is 45 bytes in this case?



    Because the FX2 will write in 23 words across the 16-bit interface, one byte will be a 'don't care' byte. One solution is to have the application on the PC side ignore the don't care byte.

    A more elegant solution is to create a protocol layer built over the firmware/hardware to communicate how many valid data values are actually contained in the packet, much like how mass storage class devices handle odd packet sizes in a CBW control wrapper.

    If the external master has apriori knowledge of byte count information, it can also switch to an 8-bit interface before writing the last byte in the odd size packet, then switch back to a 16-bit interface for successive operations.