EZ-USB FX2 Performance and Memory Size

Question: We want to use the EZ-USB FX2 (CY7C68013-56PVC) chip on our demo board. We intend to use the chip's slave FIFO I/F in synchronous mode. The interface is coupled to an FPGA for further processing. This FPGA will then be the master for the slave FIFOs. 1) How can the local transfer rate of 96 MB/s be achieved? Is it necessary to use the chip in the GPIF mode? With 48 MHz and a 16 bit data bus this would require that Ican transfer a data word (16 bit) per IFCLK cycle. But that is not possible according to Chapter 9 of the Technical Reference Manual. When I look at your example waveforms it seems at least two cycles, or actually three with "State 4", are required. How does this fit into the performance of 96 MB/s? Is it possible to transfer 16-bit data words in one cycle? Or do I need to use one cycle for reading the data, and one cycle to check the FIFO flag and update the FIFO pointer? In this case I only have a performance of 48 MB/s.  2) The setup times for read and write are almost one clock cycle when working with the 48 MHz internal IFCLK. Do I need an additional cycle to set up SLWR or SLRD? Would this further decrease the performance.?I can't see how an inverted clock would help - it makes things even worse. Unless of course I may keep the SLWR or SLRD active during e.g. a packet read where I transfer a data word on each clock cycle!?If I use an external IFCLK, according to the data sheet I get better set-up times, but then I have stronger requirements for the hold time.  3) What is the exact amount of memory inside the chip for the Endpoints EP2, EP4, EP6, and EP8? Are endpoint buffers and endpoint FIFO two separate memory areas or one? Is there a physical memory space for both the FX2 memory space (containing endpoint buffers) and additional 4KB for the FIFOs?  The way I see it, two possbilities exist: a) FX2 memory has space for 3KB (e.g 6x buffers of 512 bytes each); or b) The FIFOs have a space of 4KB. According to your data sheet, an area of 2x 512 bytes in the FX2 memory space is reserved, which explains that a buffer for EP4 and EP8 only can be 512 bytes. The FIFO space (if it is extra space?) has a total of 4KB with no reserved areas, right?  4) When exactly are full and empty flags asserted? On a byte, 16-bit word, USB packet, or user defined packet size level? I need this exact information for both reads or writes to a slave FIFO endpoint. The technical reference manual fails to offer precise information on that.



1) The burst rate of 96MB/s can be achieved by running the slave FIFOs at 48 MHz (internal or external clock), while asserting SLWR or SLRD/SLOE for the entire data burst phase. Assuming active low polarity signals, when writing to the slave FIFOs, SLWR should be held low as each word is clocked on the rising edge of IFCLK. The case is similar for reading from the slave FIFOs; SLOE/SLRD should be held low as each new word is read on every rising edge of IFCLK. The technical reference manual assumes a conservative approach as the examples show a word being clocked on every other IFCLK edge. This is for systems that may not be able to abide by the setup and hold times required for a burst phase like what's described above. Clocking a word on every other edge would then reduce the effective burst rate to 48 MB/s. FX2 has the ability to have the FIFO flags assert one word prior to the FIFO becoming full, and one word prior to the FIFO becoming empty. This give the external master additional time to check the FIFO status flags.

2) To achieve the 96MBs, the control signals will have to be active while each word is clocked on the rising edge of IFCLK.

3) The endpoints and FIFOs share one and the same physical memory space. Often you'll see them referred to as "endpoint FIFOs" because they exhibit a dual personality. There are basically two domains the endpoint FIFOs reside in, the USB domain, and the peripheral interface domain. FX2 is able to switch clock domains to pass the packet pointers from one domain to the other, thus seemingly able to "connect" the USB domain to the peripheral interface domain. This is how it maximizes the USB 2.0 bandwidth without need of processor intervention. Sometimes it's a lot easier to think of the FIFO space in terms of buffers, consistent with the different buffering schemes the FX2 can take on. The possible buffering schemes are shown on page 14 of the datasheet. Only EP2 and EP6 can be configured for the larger 1024 FIFO size.

4) The FIFO full and empty flags are byte/word based (depending on how the FIFOs are configured) and therefore represent
byte/word boundaries. For example, if the EP6 full flag is not assserted then there is room for at least one more byte/word in the FIFO. Conversely, if the EP2 empty flag is not asserted, then there is at least one more byte/word to be read by the external master.However, a user level threshold can also be defined for the programmable flag (FLAGA)