Controlling 3-Level select inputs (Example: SPDSEL) with an FPGA/CPLD output is not recommended, since the DC levels for the three level input HIGH and LOW have less noise margin than LVTTL DC levels. Moreover, controlling the FPGA/CPLD output in three-state mode to achieve the MID state for the 3-Level inputs is not a recommended practice. The noise immunity levels of three level inputs is less than the noise immunity levels of two level inputs. Using static signals ensures that the dc voltage level specification for the three level inputs are met.
For a given application, the 3-Level select control inputs are recommended to be static inputs. To achieve a HIGH state, we recommend to tie a strong pull-up (100 ohms) resistor to the 3-Level select pin. To achieve a LOW state, we recommend to tie a strong pull-down resistor (100 ohms) to the 3-Level select pin. To achieve a MID state, leave the pin floating. In the prototype design stage, customers might want to have the options for pull-up as well as pull-down resistor to provide more flexibility in their design.