HOTLink Transmitter and Receiver have completely integrated PLL clock multiplier (CMU) and data separator functions (CDR). These functions are implemented with high-performance phase-locked loops (PLLs) that have been tuned for maximum performance and minimum system noise sensitivity. In competitive products that claim to offer similar functions, these PLL's are often implemented with external filter and frequency setting components with the goal of achieving maximum performance. These very same external components are the largest cause of end-user complaints and random system failures because they expose the most critical analog signals in the circuit to the external noises that abound in normal systems. External components require critical, costly and time consuming printed circuit board layout as well as high-speed analog and digital design techniques that are unfamiliar to many system integrators. HOTLink products are designed and built using fully differential analog and digital circuits to give the lowest possible output jitter and highest possible jitter tolerance. There are no external components to compromise system performance in unexpected and unpredictable ways.
For more information, refer to the HOTLink Transmitter Jitter section of the "HOTLink Jitter Characteristics" application note.
HOTLink Transmitter/Receiver (Attached below 38-02017_0D_V)
HOTLink Jitter Characteristics -AN1161