Command Register Write Delays With CY7C68001.

Version 1
    Question: Is the maximum delay between writes to command registers 200ns? If the delay is enforced, will the READY line come out of the SX2?

     

    Answer:

    The READY pin is required in SX2 interfaces and should be monitored by the master rather than count on a timed period. This pin is an integral part of the command interface and is required to signal that the SX2 is ready to receive a new command sequence.