PCI bus and local bus during reset

Version 1


    - On the PCI bus, how is parking the bus handled?

    - When in PCI reset, what do the PCI bus pins do?

    - When powered up, what state is the local bus in?


    According to the PCI specification, when RST# is asserted, all PCI output signals must be driven to their benign states. In general, this means they must be tri-stated. Exceptions are:

    - SERR# is floated

    - To prevent the AD bus, the C/BE bus and the PAR signals from floating during reset, they may be driven low by a central resource during reset.

    On the local side, the data bus of the local bus of the PCI-DP remains in high-z during power-up (the local bus would not yet even be configured). The only times when the PCI-DP is driving data onto the DQs is when a read transaction is performed on the local bus. When this read terminates, the bus remains in high-z. The DQs remain in high impedence when reset #RST is asserted.