Why does my application fail when I run the enCoRe III CPU at 24MHz (SysClk/1), but pass at 12MHz(SysClk/2)? Are there any issues with running enCoRe III at 24MHz, is there a workaround for the issue?

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    Question: Are there any issues with running enCoRe III at 24MHz? (or) My application fails when I run the enCoRe III CPU at 24MHz (SysClk/1), but passes at 12MHz(SysClk/2)



    There is an issue with the PMA read (placing data into a RAM buffer) when CPU clock is 24MHz (SysClk/1) in enCoRe III devices. There are no known issues when running the CPU clock at 12MHz(sysClk/2) or less.



    If your application runs at a CPU clock of 24MHz(SysClk/1), it should handle PMA read operation at CPU clock = 12MHz (SysClk/2). Please add this attached file instead of the usb.asm or usbfs.asm file in your PSoC Designer Library Source. This file has the below code incorporated in it. The code provides for CPU clock change to 12MHz from 24Mhz when PMA read takes place. Also, do not do a after this change. If a is done, PSoC Designer overwrites the changes to the usb.asm/usbfs.asm file.




    This is the change that is implemented in the attached usb.asm/usbfs.asm file for the 24MHz operation.




    ;; 24Mhz read PMA workaround






        mov     A, reg[OSC_CR0]

        push    A

        and     A, 0xf8 ;clear the clock bits (briefly chg the cpu_clk to 3Mhz)

        or      A, 0x02 ;will set clk to 12Mhz


        mov     reg[OSC_CR0],A  ;clk is now set at 12Mhz



              mov     A, reg[PMA0_DR]                ; Get the data from the PMA space

              mov              [X], A                            ; save it in data array

              inc     X                              ; increment the pointer

              dec     [USB_APITemp+1]                ; decrement the counter

              jnz     .loop                          ; wait for count to zero out


    ;; 24Mhz read PMA workaround (back to previous clock speed (kvn)


        pop     A ;recover previous reg[OSC_CR0] value


        mov     reg[OSC_CR0],A  ;clk is now set at previous value (probably 24Mhz)



    ;;  end 24Mhz read PMA workaround






    We are working on updating this workaround in our user module code, so we don't have to worry about losing it everytime we generate application.