As the external peripheral wired to the SX2 is the MASTER. It can initiate transfers to the SX2: read/write request. Once the external master has initiated a read request using the command protocol as explained in section 126.96.36.199, the SX2 will buffer all the interrupts and the next interrupt triggered will only and exclusively be to signal the external master of the availability of the data for the read request.
So, the external master knows how to differentiate an interrupt (INT being asserted ) due to read request or due to an actual interrupt source (these sources are covered in section 3.4.2 (INTENABLE Register Bit Definition)). So, if the external master has not initiated any read request, then the only reason the SX2 can trigger an Interrupt is due to one of the sources (as presented in section 3.4.2). If it has initiated a register read request, then the next subsequent interrupt is unambiguously for the register read request ONLY.
Please note that in general, once a read request is initiated by the external master, the SX2 will buffer ALL inetrrupts and the next interrupt is only for the read event (read register request initiated by the external master). There is a very rare potential for a race condition when this may not be true. We highly recommend that one reads thoroughly through section 3.4.2, especially the end where it is mentioned about the way the external master may differentiate an Interrupt due to read request or an interrupt due to one of the sources and discusses the potential race condition a bit more in detail and how the external master may verify that it is not reading the wrong information by noting the state of the READY pin at the time the Interrupt occurs.