The INT line is solely dedicated to the read register after the read register command is issued by the external master. The read register sequence occurs in 3 steps
1. External master issues a read register command by providing the register address to be read.
2. SX2 puts the data from the corresponding register on FD[7:0]
3. SX2 asserts INT# pin to inform the external master that data is available on FD [7:0]
If an interrupt from any other source occurs after step1 and before step3 of the read register sequence, the SX2 will buffer that interrupt until the read request completes and the external master has read the data. This insures that after a read sequence has begun, the next interrupt that is received from the SX2 will indicate that the corresponding data is available. The other interrupt source gets buffered and will not interfere with read request. After reading the register data, the processor will be notified of the interrupt source via the INT line going low again.