External master and Data in SX2 FIFO

Question: How does the external master determine if there's data in the SX2 FIFO to be read?



There are 2 ways by which the external master can be informed if there is data in the SX2 FIFO s to be read.

1.   The external master can tell by using the interrupt signal coming from SX2. It will need to determine that it's a FLAGS interrupt by reading the status of bit 5 in the IRQ register


2.   SX2 has 4 FIFO flags (FLAG A, B, C and D) which can be programmed to represent any flag (Full flag, Empty flag, Programmable Flag) of any endpoint FIFO. This can be done by writing 4 select bits of SX2 configuration registers FLAGSAB and FLAGSCD. Program one of these flags to represent the Empty Flag of the SX2’s endpoint FIFO from which the data has to read. The external master can check the status of this flag pin to determine if there is data to be read (it has received data from host) from that endpoint FIFO of SX2.