CY7C09449PV - Basic Read/Write operations to MPC8260 processor

Version 1


    What are the settings to be taken care of when using MPC8260 processor ?


    For all local bus interactions, read and write operations have two phases: an address phase and a data phase. Most of the signals that are needed to interface with the processor are configurable through the LBUSCFG register space of the PCI-DP.

    If configuring the 32-bit Motorola for 16-bit operation, only the upper 16 bits are used. Some connection guidelines:
    - LCL_D[31:16] connected to DQ[15:0]
    - L_A[29:17] connected to ADR[14:2]
    - BW register set to 01 --> defines the bus width to 16 bits
    - BEMODE register set to 1 --> determines the byte enable encoding to operate in Motorola style

    If using all 32-bits:
    - LCL_D[31:0] connected to DQ[31:0]
    - L_A[29:17] connected to ADR[14:2]
    - BW register set to 11
    - BEMODE register set to 0 or 1 depending on how the BEs are to be used. (refer to pages 15-16 of datasheet)

    The read & write operations for both 16 and 32 bit interfaces are the same in terms of how the signals operate. The difference is in a 16 bit operation, we can divide the memory array into two banks using the BE signals.

    Basic READ operation:
    As you can see on page 20, the address phase begins when STROBE and SELECT and either READ is asserted at the rising edge of a clock with the address present on the address bus. The DQ bus is activated at the next clock edge. Depending on how long it takes both the PCI-DP and the local processor to be ready, the data phase begins when RDY_IN#, RDY_IN, and RDY_OUT# are all asserted. At this edge, the BEs are examined and the proper data is output onto the DQ bus. Read operations are allowed until the BLAST signal signifies the last burst read.

    Basic WRITE operation:
    The write operation begins with the same address phase as before except WRITE is asserted (or READ is deasserted) during a rising edge. Again, all 3 ready signals must be asserted with the data on the bus for the PCI-DP to latch the data. Bursting is allowed until BLAST signifies the last burst write.

    For additional information about the local processor side, please refer to pages 12-26 of the datasheet: