There are some restrictions on device clocking, and software workarounds required, if low power operation is to be possible in ES2 silicon. These restrictions will be addressed in future releases of PSoC silicon revisions (after ES2).
1. MASTER_CLK must be sourced from the IMO
You may not use XTAL, PLL_OUT or a digital signal with low power modes.
This is set in Clocks tab of the CYDWR file.
2. For IMO frequencies above 12MHz you may not use a clock divider of 1
For IMO frequencies of 3MHz, 6MHz and 12MHz all divider values for MASTER_CLK are legal. For IMO frequencies of 24MHz and 48MHz all divider values except 1 are legal. This is set in Clocks tab of the CYDWR file.
3. You must define the macro CYLIB_POWER_MANAGEMENT
In order for the sleep APIs to be generated this macro must be defined on the compiler command line. This is set in the Compiler section of the Build Settings for the project.
4. The ADC_DelSig component needs to reset the decimator CR register
The decimator CR register is not preserved in low power modes. To re-start an ADC_DelSig component run the following line of code after the device wakes up:
_DEC_CR = __DFLT_DEC_CR;
Note the double underscore before "DFLT".
5. Component _Start() APIs do not fully re-initialize the hardware.
On exiting a low power mode you need to force a full re-initialization of the component. To do this declare the following variable as shown in the following line of code:
Then execute the following line of code after the device wakes up:
_initvar = 0;
The affected components are: