The skew can be measured with a particular configuration and there are techniques to minimize it as mentioned below. However, it cannot be predicted for this part as different frequency configurations are possible which will vary the value. For the CY22293, there is an individual divider for each output. The output dividers are always clocked on the rising edge of reference source. There is NO synchronization circuitry included for different dividers. So when the outputs reference from the same PLL with dividers, they may NOT be phase aligned. CY22150is a single PLL based device having limitations on the different frequency combinations at the outputs with a particular reference. Also, it does not have a divider of 1.
The outputs will be phase aligned if the outputs reference the same PLL and bypass the output divider (set it to 1). There is also another option, if the output references the same PLL and the divider values are related to each other only by a factor of 1.
If loading is different on the outputs, the skew will be different. If you have different transmission line lengths at the outputs, the reflections will make a round trip in a different time, which may affect this skew. If different frequencies are being output simultaneously, or the noise environment and/or coupling between outputs is different, you can get changes in output skew. Etc...
Ganging outputs is one way to reduce output-output skew with same frequency values. Other "tricks" to minimize output-output skew are as follows:
1. Keep same length transmission lines at output.
2. Allow only one frequency output simultaneously (if possible).
3. Use same Vdd on all output buffers (this will help reduce part to part skew).
4. Terminate outputs in same way.
5. Route outputs in most symmetrical way possible.
We have our Layout Recommendations for the CY2239x Devices - AN1109, available on our website, for your assistance.