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I2C Clock Permanently Stuck To Logical Low
Anonymous
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Oct 08, 2009
02:32 AM
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Oct 08, 2009
02:32 AM
Answer:
Question: Why PSoC permanently holds SCL line low after it sends an ACK to a received address byte ?
Response: Details given below,- Caused due to a bug in EzI2C user module code
- Found in EzI2C user module version 1.2 shipped with PSoC Deisgner 5 SP5
- Solution to this problem is to replace existing 'EzI2Csint.asm' template file from below locations with the one attached with this KB article,
- C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\CY8C20060\EzI2Cs
- C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\psoc_0100\EzI2Cs
- C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\Stdum\EzI2Cs
- I2C SCL line is stretched to logic zero permanently from the PSoC side soon after master send a data byte following an address byte
- Address byte send by the master is ACK'ed by the PSoC even if it is not its address
- Refer the attached 'pdf' file for details
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