We normally recommend the following steps to dynamically update the PLL:
For PLL2 or PLL3:
1. Disable the PLL by setting the PLL*_En bit low.
2. Reprogram the P, Q, and PLL*_LF values.
3. Enable the PLL by setting the PLL*_En bit high.
PLL1 is different from PLL2 and PLL3. It has a frequency table which is controlled by the S2, (S1, S0) pins. The SCLK/S1 and SDAT/S0 pins are latched inputs and depending on how they are held at power up, will determine which table entries are accessible during operation. Normally there are pull-ups on the I2C data and clock lines. With pull-ups on the SCLK/S1 and SDAT/S0 pins, during operation a user can access the  and  table entries by toggling the S2 pin. When switching between table entries with the S2 pin the clock outputs will slew to the new frequency without glitching when the output divider values are only changed, not the P and Q divider values.
For example assume the user is using PLL1 table entry  then toggling S2 high will access 
1. Since  is in current use the user will edit the PLL values at address 55H-57H (Table entry for ).
2. Once address 55H-57H is configured, toggle the S2 pin high to access the  entry and new frequency.
3. If another frequency change is required, change the PLL values at address 49H-4BH (Table entry for ).
4. Once address 49H-4BH is configured, toggle the S2 pin low to access the  entry and new frequency.