Preserve RAM contents during M8C or WDT Reset

Answer:

Question: How do I preserve the contents of RAM when a Watch Dog Timer (WDT) Reset or SWBootReset (Software Reset) has occured? 

Response: Figure below shows the state of the SRAM registers in Page-0 when a Watchdog or SWBootReset occurs.

'xx' - Indicates that the content of these SRAM locations is not modified by the reset.
'00' - Indicates that the content of these SRAM locations will be reset to 0x00.
'??' - Indicates that the state of these SRAM locations is determined by the state of the IRAMDIS bit in the CPU_SCR1 register.  If this bit is set to 1, the content of these locations will not be modified.  If the bit is 0, the content of these locations will be reset to 0x00.

So, to preserve the RAM content on a Reset event, set the IRAMDIS bit in the CPU_SCR1 register.  But remember, only the locations marked '??' will be preserved.

For more details, please refer to the SWBootReset Function of Supervisory ROM in the TRM.