You can 'disable' the CPLD by assigning all outputs of the design as High Z, using an asynchronous condition. For example, if your code has a process (VHDL) that puts an address and data on the bus, you should use an if clause to tristate the bus at the beginning of this process. 'mstreset' is an input std_logic signal you have to declare.
process (mstreset, address, data, inputs) -- sensitivity list
if (mstreset = '0') then -- active low
address <= "ZZZZZZZZZZZZZZZZ" -- assuming a 16-bit address bus declared as std_logic_vector input
data <= "ZZZZZZZZ"; -- assuming an 8-bit data bus declared as std_logic_vector input
...rest of your code that performs the function.
Please note that this does not actually disable the CPLD. It is only a way by which you can tristate all the signals driven by the CPLD. So in effect, the CPLD still is working without affecting other parts on the board. Unused outputs of the CPLD can be set to Z in the Compiler options.
Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development.