PLL stands for Phase locked loop and DLL stands for Delay locked loop.
A PLL/DLL is implemented on QDRII/II+/DDRII /II+ SRAMs with the purpose of placing the output data coincident with the rising edge of the input clocks—C and Cb clocks, if supplied, otherwise K and Kb clocks.
The 65nm technology QDRII/II+/DDRII /II+ SRAMs have a PLL inside the device whereas the 90nm technology QDRII/II+/DDRII /II+ SRAMs have a DLL inside the device.
The PLL filters the incoming jitter and corrects any duty cycle distortion for the inputs. This results in improved data valid window and helps achieve better timing margins for the 65 nm technology device.
The data valid window for the outputs of 65 nm QDR devices is about 21% wider than the 90 nm QDR devices. This improvement is achieved using a low jitter clock generating PLL (Phase Locked Loop) as opposed to a DLL (Delay Locked Loop) in the 90 nm technology.