In PSoC3/5 I/O’s are divided into four quadrants. The pins Vddio0, Vddio1, Vddio2 and Vddio3 are used to control the I/O voltage of each quadrant respectively. Hence each quadrant can be configured to have a different threshold level. Therefore even if the device is operating at 5V, an I/O port can be configured for a threshold voltage of 3.3V and thereby can be interfaced with an external device operating at 3.3V.
The Vddio pins should be supplied with a reference voltage in order to control the I/O threshold voltage. In PSoC3/5 this threshold voltage can be generated inside the chip itself. A voltage DAC (VDAC) is used to generate the required reference voltages. The VDAC output is passed through an Opamp buffer to increase the drive strength (25mA source/sink for entire quadrant).
The advantage of this method is that the voltage DAC provides 8 bits of programmability to the reference voltage. Hence the threshold voltage of I/O’s can be varied during runtime.
The diagram showing the required connections are as follows:
The diagram shows configuring the threshold level of the Quadrant 0 (Vddio0). The Opamp output is routed to P3 which belongs to Quadrant 3. The Quadrant 3 will be powered by the device voltage (Vdd = 5V, by leaving pin Vddio3 open). The Blue line shown above implies an external wire connection.