The SC blocks output is valid only during one of the phases (phi1 or phi2) of the column clock and is equal to the opamp offset voltage during the other phase. So, if a DAC output is directly connected to the reference of the comparator, the output of the comparator will not be stable. The same problem applies to any application where the output of an SC block is directly connected to a CT block.
The solution to this problem is to route the SC block output through the analog bus. The analog bus of each column has a sample and hold circuit with a 1.4pF capacitor which provides a steady output from the SC block.