Interrupt can be disabled during debugging by writing to the register ‘NVIC.CLRENA0: 0xE000E180’ (32 bits)(in case of PSoC5) and INTC_CLR_EN:0x44c8(8 bits)(in case of PSoC3). For further detail, please refer to the register TRM of PSoC3 or PSoC5.
To write to these register, please follow the following steps-
->Click on debugging tab.
->Debugging and memory window will open.
-> Go to the memory window and update the memory space (0xE000E180 for PSoC 5 or 0x44c8 for PSoC3).
To disable the interrupt, write 0xffff in the NVIC.CLRENA0: 0xE000E180 register in case of PSoC5 and 0xff in the INTC_CLR_EN:0x44c8 register in case of PSoC3.