Question: How do I generate VREF and VTT in QDR®, DDR-II, DDR-II+, and Xtreme SRAM devices?
The different supply voltages required for DDR and QDR devices are as follows:
- VDD - Core voltage (1.8 V typical)
- VDDQ - Supply voltage for I/Os (1.4 V to VDD)
- VREF - Reference voltage for HSTL inputs(VDDQ/2)
- VTT - Termination voltage(VDDQ/2)
VREF is a reference voltage that provides a DC bias of VDDQ/2 for the differential HSTL input buffers. Noise or deviation in the VREF voltage can lead to potential timing errors, unwanted jitter, and erratic behavior on the memory bus.
Because of the power-up sequence in the DDR and QDR SRAM devices, VDDQ must be applied before or at the same time as the
application of VREF.
You can generate VREF from VDDQ using one of the following methods:
- Voltage divider arrangement
- VREF and VTT generation using termination regulator ICs
Ensure that the VREF source tracks variations in VDDQ due to temperature and noise. A brief description of both the methods follows:
Voltage divider arrangement
VREF can be generated from VDDQ by using a resistor divider as shown in the following figure. Both resistors must be of the same value (typical 1 KΩ) and 1% tolerance.
Figure 1: VREF Generation from VDDQ using a Resistor Divider
VREF and VTT generation using termination regulator ICs.
VTT is the termination voltage. Both VREF and VTT must share a common source supply, VDDQ. There are numerous off-the-shelf power IC solutions, such as TPS51100 and LP2995, that provide both the VREF and VTT from a common source.
Figure 2. VTT and VREF Generation using Termination Regulator IC.
The VREF current for the 65-nm QDR, DDR-II, DDR-II+, and Xtreme devices is about 100 uA, because these pins drive the gates of transistors. The VREF and VTT pins should have decoupling capacitors close to the memory devices for best results. For more details, refer to the knowledge base article, Reference Schematic Design Recommendation for QDR®-DDR II/II+/Xtreme SRAMs - KBA84386.