The logic that determines the current state of the FIFO is driven by the relationship between the read pointer and write pointer in the device. The master reset process ensures that upon power-up, these pointers are aligned properly. If it seems as if these flags are behaving incorrectly, then it very likely that there was a problem with the master reset and the pointers are misaligned. This could be the result of a noise pulse on the /MR signal, or timing for the master reset was not satisfied. Please refer to the appropriate datasheet to find the timing considerations for a proper reset. If there is still a problem, use an oscilloscope, not a logic analyzer, to see whether there is noise on the /MR, /R, or /W signals.