PSoC 3 ADC is a fully differential ADC and gives its output in the 2’s complement format. Single ended mode is implemented by connecting the negative input to vssa and by ignoring the sign bit. When the offset of the device is negative, say -0.1mV the differential ADC will produce an output or FFFC/FFFD (in 16-bit mode). Since the single ended output is treated as an unsigned number, whenever the device has a negative offset, shorting the inputs will give you a value close to full scale even though the ADC is configured for single ended measurement.
The way to avoid this is by adding a small positive offset in firmware. Remember, the dynamic range comes down by the amount of software correction made. This phenomenon is observed only if the device has a negative offset. It is not present if the offset is positive.