The NV latch stores the power on state of a GPIO pin. If the pin state is selected as a non-default state, the NV Latch will be reprogrammed everytime the program is downloaded to the device. The data endurance of NV Latch for PSoC3 ES2 silicon is only 10 read/erase cycles.
So, while using the PSoC3 ES2 silicon, during the development phase of a design, it is recommended not to modify the reset state of a pin. If you still need to configure the reset state of the pins, follow the below procedure to minimize the number of NV Latch erases.
1. Configure the power on reset state of all the pins in the design.
2. Build the project and program the device. This will result in the NV Latch being programmed with the POR reset state of the pins.
3. After downloading the program, set the power on reset state of all the pins back to "Don't Care". Now further program downloads will not modify the NV Latch and the pins will remain in the state programmed in step 2. In the .cydwr file, lock the pins that have been configured so that PSoC Creator does not move the pins.
However, the NV Latch data endurance for PSoC3 production silicon will be 10,000.