Use the following procedure to set the CPU speed of PSoC 3 to maximum (67MHz) (or any other desired frequency).
1. Open the .cydwr file in the project.
2. In the Clocks tab, select MASTER_CLK and click on the Edit Clock button.
3. In the PLL box, select IMO as the clock source and set desired frequency to 67MHz.
4. In the Master Clock box, select PLL_OUT as the source, and set a divider of 1.
5. Similarly set the divider to 1 in the Bus Clock box.
Below screen shot shows the clock configuration.
The maximum allowed CPU frequency for PSoC3 is 67MHz. PLL can be used to generate this high frequency from low frequency sources like IMO, ECO or Digital Signal. But the accuracy of 67MHz PLL output will depend on the accuracy of these low frequency sources. If the low frequency sources are having an accuracy of +/-0.1%, then the PLL output will also have the same accuracy. +/-0.1% of 67MHz will correspond to 66.933 to 67.067MHz which may exceed slightly the allowable CPU frequency. So this is the reason why we are getting the following error message when trying to set PLL output to 67MHz
So, the maximum allowed PLL output frequency in PSoC3 is 66MHz