We can use the IMO clock for UART communication provided the IMO clock is configured for 3MHz, or 6MHz. We can use the IMO with PLL to get UART operation at full speed. The reason for the clock frequency limitation is explained below.
PSoC 3/5 UART uses 8x clocking for receive state machine, and it means the receive logic samples the input at 8x times the baud rate. The UART data frame consist of 10 bits viz., 1 start bit, 8 data bits, and 1 stop bit. The receiver is synchronized at the falling edge of the start bit; the worst case timing error will be at the stop bit.
The worst case timing error to receive the stop bit correctly is half bit period as the receiver samples the incoming bits in the middle of the bit period. The stop bit is 76 (9.5x8) UART clocks from the start bit. Half bit period translates to 4 UART clock periods in 8x clocking scheme. There will be 1 clock error due to synchronization and allowing for 1 clock period for other errors, the UART can tolerate 2 clock cycle errors over 76 UART clock cycles. This translates to 2.6% (2/76) mismatch between transmit and receive clocks. Hence, the worst case clock mismatch between UART Transmit and UART receive node has to be +/-2.6% for the UART to work correctly,
Assuming that PC UART clock is ideal, we can tolerate 2.6% error to communicate with PC. The IMO provides 1% accuracy at 3Mhz and 2% accuracy at 6Mhz. Therefore we can use IMO for UART communication at 3 Mhz / 6 Mhz configuration.