Question: What is coherency byte in ADC result register and DFB staging/holding register?
Answer: The ADC result registers are protected on reads so that the underlying hardware does not update it when partially read by CPU or DMA. When CPU/DMA is reading 24-bit ADC result (3 bytes) as multiple byte read operation, it is possible for ADC to overwrite the result register with a new samples while the CPU/DMA is reading the current sample. To avoid this problem, ADC module allows the user to specify the coherency byte using DEC_COHER[SAMP_KEY<1:0>] bits. If any byte of ADC result register is read by CPU/DMA, it will lock the result register from being overwritten untill the coherancy byte is read. Depending on the configuration of the block, not all bytes of the result registers may be needed. The coherency methodology allows for any size output field and handles it properly.
The Digital Filter Block (DFB) provides two 24-bit staging register for data input and two 24-bit holding register for data output. The DFB Staging registers are protected on writes so the DFB doesn’t incorrectly use the data when it is partially updated by the CPU or DMA. The Holding registers are protected on reads so that the DFB doesn’t update it when partially read by the CPU or DMA. Depending on the configuration of the block, not all bytes of the Staging/Holding registers may be needed. The coherency methodology allows for any size output field and handles it properly.
DFB_COHER[STGA_KEY<1:0>] bits specify the coherency byte for DFB Staging Register A
DFB_COHER[STGA_KEY<1:0>] bits specify the coherncy byte for DFB Staging Register B
DFB_COHER[HOLDA_KEY<1:0>] bits specify the coherency byte for DFB Holding Register A
DFB_COHER[HOLDB_KEY<1:0>] bits specify the coherncy byte for DFB Holding Register B
Refer to the following Appnote that set the ADC coherancy to high bytes for 24-bit ADC data transfer through DMA. Note that by default coherancy is set to low byte.
AN61102 - ADC Data Buffering using DMA
Refer to the following Example projects that set the DFB coherancy to middle bytes.
CE58352 - FIR Filter with 8-bit Streaming
CE58353 - ADC to Filter - Dual Channel 16 bit Streaming using DMA
