Up to 33 CPU clocks.
An interrupt will not be recognized while the Global Interrupts are disabled. Global interrupts are disabled in three different ways. By clearing the Global Interrupt enable bit (using the M8C_GlobalIntEn macro), when an interrupt is serviced Global Interrupts are automatically disabled, and when Supervisor code (the SSC instruction) is exectuted. So, to begin with there can be a period of time before the interrupt is recognized. This will depend on what other interrupts are occurring and how long their Interrupt Service Routines (ISR) take to execute.
From the time that the interrupt is recognized the following happens:
1) The current instruction is completed. The worst case for this would be if an INDEX instruction had just been started. The INDEX instruction takes 13 CPU clocks to exectute.
2) The current status (Instruction Counter, Flags, etc.) is saved on the stack and the interrupt vector location is jumped to. This takes 13 CPU clocks.
3) At this point, the CPU is at the interrupt table found in BOOT.ASM. Normally, this table has a LJMP (7 CPU clocks).