Data Retention Procedure for Async SRAM's

Question: I am designing a battery backed up SRAM and RTC using Cypress Async SRAM (E.g. CY62128). I will use a supercap for several days of backup time. Should I pull up /CE, /WE, and /OE to VccBATT? What else should be taken into consideration?



It is sufficient to pull up /CE1. This will ensure that the chip is deselected. You can use any one of the Chip enable pins(/CE1 or CE2) to select or deselect the chip. In this case, if you want to use /CE1 to deselect the chip, then leave the CE2 pin connected HIGH always. You don't have to control /WE and /OE when /CE is pulled up, but make sure that /WE and /CE are not toggling or the device might consume some current. Vcc should not drop to 0V to retain the data. It can only drop to the minimum possible voltage at which the SRAM can retain the data (as mentioned in the data retention mode characterstics in the datasheet). Also, /CE should be pulled up before lowering the voltage to Vcc.