The transmission speed is dependent on the I2C Master because the Master generates the clock for the communication. So there is no error in transmission speed introduced by the PSoC Slaves. But the I2C Slave stalls the SCL line before sending the ACK or NAK on each byte. The duration of the stall will depend on the CPU speed at which the PSoC is operating. This will affect the overall data transfer rate.
For more information on clock streting timings please refer to the article PSoC I2C Block Clock Stretching: Worst Case Duration.